FIG. 1 shows a plurality of communication channels 14(x) for communicating data between a first device 10 and a second device 12. In one embodiment the devices 10 and 12 can comprise discrete integrated circuits, such as a Synchronous Dynamic Random Access Memory (SDRAM) and a microprocessor in one example. In this example, communication channels 14(x) would typically comprise traces in a printed circuit board (PCB) 15. Alternatively, devices 10 and 12 could comprise circuit blocks in a planar configuration on a common substrate, with channels 14(x) comprising traces on the substrate. In yet another alternate configuration, the devices 10 and 12 might be integrated vertically (stacked) into a single package.
The communication channels 14(x) as illustrated are bidirectional, allowing data to be sent from device 10 to device 12 and vice versa. When data is sent from device 10 to device 12, the transmitters TX are activated in device 10 and the receivers RX are activated in device 12. Likewise, when data is sent from device 12 to device 10, the transmitters TX are activated in device 12 and the receivers RX are activated in device 10.
As shown, each of the illustrated communication channels 14(x) are “single-ended,” meaning that the transferred data only appears at one point in a given receiver, RX. By contrast, other communication channels in the art are fully differential, meaning that data and its complement are transferred on two traces, with both the true and complement data values being received at a differential receiver. See, e.g., U.S. patent application Ser. No. 11/972,209, filed Jan. 10, 2008.
The received data at each receiver RX, typically implemented as amplifiers, is compared to a reference voltage, Vref. As is well known in such single-ended applications, Vref comprises a threshold, such that data having a higher voltage than Vref is interpreted by the receiver RX as a logic ‘1’, while data having a lower voltage than Vref is interpreted as a logic ‘0’. The comparison of the data and Vref at the receivers is sometimes known in the art as a “pseudo differential” approach, owing to the fact the Vref is a mere threshold voltage, rather than a data complement.
Limited pin count, lower power, and the availability of legacy design work motivate the effort to increase the bandwidth of, and hence prolong the life of, single-ended signaling. While most single-ended signaling innovation targets either noise reduction through encoding techniques and supply insensitive circuit design, or bandwidth enhancement through equalization, comparatively little attention been given to techniques for reference voltage (Vref) generation, an important parameter that impacts the voltage and timing margins of the communication channels. Previous approaches to Vref generation as have occurred historically in the development of DDR SDRAM technologies are discussed in U.S. patent application Ser. No. 12/359,299 (“the '299 application”), filed Jan. 24, 2009, which is incorporated herein by reference in its entirety, and with which familiarity is assumed.
Regardless of whether Vref is generated on the PCB 15 and sent to both of devices 10 or 12, or whether Vref is generated by each of those devices internally, FIG. 2A provides a typical Vref generator 16 comprising a voltage divider formed by resistances Ra and Rb. As discussed in the '299 application, Ra and Rb can be adjustable, and such adjustability can be of particular benefit when the signals transmitted on the channels 14 are referenced to either of the I/O power supplies Vddq or Vssq. As one skilled in the art will understand, I/O power supplies Vddq and Vssq are isolated from the corresponding power supplies Vdd and Vss, which are used internal to the devices 10 and 12. Thus, Vddq and Vssq typically only provide power to the off-chip interface circuitry, whereas Vdd and Vss power the remainder of the circuitry. Dividing the power domains in this manner helps to keep noise in the communication channels 14(x) from affecting internal signaling such as internal transmitted and received data signals DXx and DRx referenced to the Vdd/Vss domain (FIG. 1). Vddq and Vssq are often shared between the devices 10 and 12 in a typical communication system, as shown in FIG. 1.
Power supply-referenced signaling is shown in FIG. 3. Circuit trace 25 shows an example of Vddq-referenced signaling, in which data states are generated with respect to Vddq at the various transmitters TX, with a logic ‘1’ equaling Vddq (perhaps with slight negligible degradation δ), and logic ‘0’ equaling Vddq−Δ, which value will generally be higher than Vssq by an appreciable amount. Trace 25 is sometimes referred to as high common mode signaling. Circuit trace 26 shows an example of Vssq-referenced signaling, in which data states are generated with respect to Vssq at the various transmitters TX, with a logic ‘0’ equaling Vssq (again, perhaps with some negligible degradation δ), and logic ‘1’ equaling Vssq+Δ, which value will generally be lower than Vddq by an appreciable amount. Trace 26 is sometimes referred to as low common mode signaling. In either case, the power supply-referenced signaling illustrated comprises a reduced swing signal, because while the voltage level for one of the logic states is essentially at the referenced supply, the voltage level for the other logic states is well short of the non-referenced supply.
If Ra and Rb are adjustable in Vref generator 16, then Vref can generally be set to the middle of the two logic states to allow proper sensing of the power supply-referenced signals at the receivers RX. For example, if Vddq-referenced signaling is used, Vref(h) can be set at approximately Vddq−½Δ, ignoring any degradation; if Vssq-referenced signaling is used, Vref(1) can be set at approximately Vssq+½Δ, again ignoring any degradation.
The Vref generator 16 of FIG. 2A produces a reference voltage Vref that scales with a difference in the I/O power supplies, such that Vref=m*(Vddq−Vssq), with m=(Rb/(Ra+Rb)). Scaling of Vref with respect to Vddq and Vssq is beneficial when either Vddq-referenced or Vssq-referenced signaling is used, because any perturbations on Vddq or Vssq would tend to manifest in the generated Vref, thus facilitating data sensing at the receivers RX. Consider Vddq-referenced signaling: if Vddq dips low for a moment, then both the voltages for a logic ‘1’ (essentially Vddq) and a logic ‘0’ (Vddq−Δ) generated at the transmitters TX will also dip low. However, Vref (Vddq−½Δ) will likewise dip low, and therefore the perturbations in Vddq are canceled out at the receivers RX. Similarly, consider Vssq-referenced signaling: if Vssq spikes high for a moment, then both the voltages for a logic ‘1’ (Vssq+Δ) and a logic ‘0’ (essentially Vssq) generated at the transmitters TX will also spike high. However, Vref (Vssq+½Δ) will likewise spike high, and therefore the perturbations in Vssq are canceled out at the receivers RX. In either case, because the generated Vref value tracks both Vddq and Vssq, either Vddq- or Vssq-referenced signaling can be used.
Because certain degradations discussed in the '299 application can cause the shape of the “data eye” of the transmitted data to vary from ideal levels, the Vref resulting from the generator 16 of FIG. 2A may not be optimal, and it may not be optimal to position Vref exactly at the midpoint between the voltages for a logic ‘0’ and ‘1’. To allow for more particularized tuning of Vref in light of such degradations, and as shown in FIG. 2B, the '299 application proposes a Vref generator 30 which adds a scalable offset, b. An adjustable current source 32 is used to adjust the offset b between the power supplies and Vref, while adjustable resistors Ra and Rb are used to adjust the slope m between the power supplies and Vref as in the prior art, such that Vref=m*(Vddq−Vssq)+b, or Vref=m*Vddq+b if Vssq is assumed as zero. Similarly to FIG. 2A, the Vref value of FIG. 2B tracks both Vddq and Vssq, which facilitates sensing as discussed above.
While these previous approaches to Vref generation can be put to good use in a particular application, the inventor has noticed that they do not provide an optimal solution for every conceivable communication system, particularly one in which one of power supplies Vddq or Vssq are not shared between the devices 10 and 12. This disclosure provides an improved Vref generator design for such a communication system.